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november 2012 ? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan2106 ? rev. 1.1.2 fan2106 ? tinybuck? 3-24v input, 6a, high-effi ciency, integrated synchronous buck regulator fan2106 ? tinybuck? 3-24 v input, 6 a, high-efficiency, integrated synchronous buck regulator features ? 6 a output current ? wide input range: 3 v - 24 v ? output voltage range: 0.8 v to 80% v in ? over 95% peak efficiency ? 1% reference accuracy over temperature ? programmable frequency operation: 200 khz to 600 khz ? fully synchronous operation with integrated schottky diode on low-side mosfet boosts efficiency ? internal bootstrap diode ? internal soft-start ? power-good signal ? starts on pre-biased outputs ? accepts ceramic capacitors on output ? external compensation for flexible design ? programmable current limit ? under-voltage, over-voltage, and thermal protections ? 5x6 mm, 25-pin, 3-pad mlp package applications ? servers & telecom ? graphics cards & displays ? computing systems ? point-of-load regulation ? set-top boxes & game consoles description the fan2106 tinybuck? is a highly efficient, small- footprint, constant-fr equency, 6 a, integrated synchronous buck regulator. the fan2106 contains both synchronous mosfets and a controller/driver with optimized interconnects in one package, which enables designers to solve high- current requirements in a small area with minimal external components. integr ation helps to minimize critical inductances, making component layout simpler and more efficient compar ed to discrete solutions. the fan2106 provides for external loop compensation, programm able switching frequency, and current limit. these features allow design flexibility and optimizati on. high-frequency operation allows for all-ceramic solutions. the summing current-mode modulator uses lossless current sensing for current feedback and over-current protection. voltage feedforward helps operation over a wide input voltage range. fairchild?s advanced bicmos power process, combined with low-r ds(on) internal mosfets and a thermally efficient mlp pack age, provide the ability to dissipate high power in a small package. output over-voltage, under-v oltage, over-current, and thermal shutdown protections help protect the device from damage during fault conditions. fan2106 prevents pre-biased output di scharge during startup in point-of-load applications. related resources ? an-8022 ? tinycalc? calculator user guide ? tinycalc? calculator design tool ordering information part number operating temperature range package packing method fan2106mpx -10c to 85c molded leadless package (mlp) 5x6 mm tape and reel fan2106empx -40c to 85c molded leadless package (mlp) 5x6 mm tape and reel
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan2106 ? rev. 1.1.2 2 fan2106 ? tinybuck? 3-24v input, 6a, high-effi ciency, integrated synchronous buck regulator typical application diagram figure 1. typical application block diagram figure 2. block diagram
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan2106 ? rev. 1.1.2 3 fan2106 ? tinybuck? 3-24v input, 6a, high-effi ciency, integrated synchronous buck regulator pin configuration figure 3. mlp 5x6 mm pin configuration (bottom view) pin definitions pin # name description p1, 6-12 sw switching node . junction of high-side and low-side mosfets. p2, 2-5 vin power input voltage . connect to the main input power source. p3, 21-23 pgnd power ground . power return and q2 source. 1 boot high-side drive boot voltage . connect through capacitor (c boot ) to sw. the ic includes an internal synchronous bootstrap diode to re charge the capacitor on this pin to v cc when sw is low. 13 pgood power-good flag . an open-drain output that pulls low when fb is outside the limits specified in electrical specs. pgood does not assert high until the fault latch is enabled. 14 en enable . enables operation when pulled to logic high or left open. toggling en resets the regulator after a latched fault condition. this input has an internal pull-up when the ic is functioning normally. when a latched fault occurs, en is discharged by a current sink. 15 vcc input bias supply for ic . the ic?s logic and analog circuitry are powered from this pin. this pin should be decoupled to agnd through a >1 f x5r/x7r capacitor. 16 agnd analog ground . the signal ground for the ic. all internal control voltages are referred to this pin. tie this pin to the ground isl and/plane through the lowe st impedance connection. 17 ilim current limit . a resistor (r ilim ) from this pin to agnd can be used to program the current- limit trip threshold lower than the default setting. 18 r(t) oscillator frequency . a resistor (r t ) from this pin to agnd sets the pwm switching frequency. 19 fb output voltage feedback . connect through a resistor di vider to the output voltage. 20 comp compensation . error amplifier output. connect the ex ternal compensation network between this pin and fb. 24 nc no connect . this pin is not used. 25 ramp ramp amplitude . a resistor (r ramp ) connected from this pin to vin sets the ramp amplitude and provides voltage feedfor ward functionality.
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan2106 ? rev. 1.1.2 4 fan2106 ? tinybuck? 3-24v input, 6a, high-effi ciency, integrated synchronous buck regulator absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the devic e may not function or be operable above the recommended operating c onditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stre sses above the recommended operating conditi ons may affect device reliability. the absolute maximum ratings are stress ratings only. parameter conditions min. max. unit vin to pgnd 28 v vcc to agnd agnd = pgnd 6 v boot to pgnd 35 v boot to sw -0.3 6.0 v sw to pgnd continuous -0.5 24.0 v transient (t < 20 ns, f < 600 khz) -5.0 30.0 all other pins -0.3 v cc +0.3 v esd human body model, jedec jesd22-a114 2.0 kv charged device model, jedec jesd22-c101 2.5 recommended operating conditions the recommended operating conditions table defines the conditions for actual device oper ation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specificat ions. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter conditions min. typ. max. unit v cc bias voltage vcc to agnd 4.5 5.0 5.5 v v in supply voltage vin to pgnd 3 24 v t a ambient temperature fan2106mpx -10 +85 c fan2106empx -40 +85 t j junction temperature +125 c f sw switching frequency 200 600 khz thermal information symbol parameter min. typ. max. unit t stg storage temperature -65 +150 c t l lead soldering temperature, 10 seconds +300 c jc thermal resistance: junction-to-case p1 (q2) 4 c/w p2 (q1) 7 p3 4 j-pcb thermal resistance: juncti on-to-mounting surface 35 (1) c/w p d power dissipation, t a = 25c 2.8 (1) w note: 1. typical thermal resistance when mount ed on a four-layer, two-ounce pcb, as shown in figure 26. actual results are dependent on mounting method and surf ace related to the design.
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan2106 ? rev. 1.1.2 5 fan2106 ? tinybuck? 3-24v input, 6a, high-effi ciency, integrated synchronous buck regulator electrical specifications electrical specifications are the result of using the circuit shown in figure 1 with v in = 12 v, unless otherwise noted. parameter conditions min. typ. max. unit power supplies v cc current sw = open, fb = 0.7 v, v cc = 5 v, f sw = 600 khz 8 12 ma shutdown: en = 0, v cc = 5 v 7 10 a v cc uvlo threshold rising v cc 4.1 4.3 4.5 v hysteresis 300 mv oscillator frequency r t = 50 k 255 300 345 khz r t = 24 k 540 600 660 khz minimum on-time (2) 50 65 ns ramp amplitude, peak-to-peak 16 v in , 1.8 v out , r t = 30 k , r ramp = 200 k 0.53 v minimum off-time (2) 100 150 ns reference reference voltage (v fb ) (3) fan2106mpx, t a = 25c 794 800 806 mv fan2106empx, t a = 25c 795 800 805 mv error amplifier dc gain (2) v cc = 5 v 80 85 db gain bandwidth product (2) 12 15 mhz output voltage (v comp ) 0.4 3.2 v output current, sourcing v cc = 5 v, v comp = 2.2 v 1.5 2.2 ma output current, sinking v cc = 5 v, v comp = 1.2 v 0.8 1.2 ma fb bias current v fb = 0.8 v, t a = 25c -850 -650 -450 na protection and shutdown current limit r ilim open, f sw = 500 khz, v out = 1.8 v, r ramp = 200 k , 16 consecutive cycles 6 8 10 a i lim current v cc = 5 v, t a = 25c -11 -10 -9 a over-temperature shutdown internal ic temperature +155 c over-temperature hysteresis +30 c over-voltage threshold 2 cons ecutive clock cycles 110 115 120 %v out under-voltage shutdown 16 consec utive clock cycles 68 73 78 %v out fault discharge threshold measured at fb pin 250 mv fault discharge hysteresis measured at fb pin (v fb ~500 mv) 250 mv soft-start v out to regulation (t0.8) frequency = 600 khz 5.3 ms fault enable/ssok (t1.0) 6.7 ms continued on the following page?
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan2106 ? rev. 1.1.2 6 fan2106 ? tinybuck? 3-24v input, 6a, high-effi ciency, integrated synchronous buck regulator electrical specifications (continued) electrical specifications are the result of using the circuit shown in figure 1 with v in = 12 v, unless otherwise noted. parameter conditions min. typ. max. unit control functions en threshold, rising v cc = 5 v 1.35 2.00 v en hysteresis v cc = 5 v 250 mv en pull-up resistance v cc = 5 v 800 k en discharge current auto-restart mode, v cc = 5 v 1 a fb ok drive resistance 800 pgood threshold (compared to v ref ) fb < v ref , 2 consecutive clock cycles -14 -11 -8 %v ref fb > v ref , 2 consecutive clock cycles +7 +10 +13 %v ref pgood output low i out < 2 ma 0.4 v note: 2. specifications guaranteed by design and characteri zation; not production tested. 3. see figure 4 for temperature coefficient
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan2106 ? rev. 1.1.2 7 fan2106 ? tinybuck? 3-24v input, 6a, high-effi ciency, integrated synchronous buck regulator typical characteristics 0.990 0.995 1.000 1.005 1.010 -50 0 50 100 150 temperature ( o c) v fb 0.80 0.90 1.00 1.10 1.20 -50 0 50 100 150 temperature ( o c) i fb figure 4. reference voltage (v fb ) vs. temperature, normalized figure 5. reference bias current (i fb ) vs. temperature, normalized 0 300 600 900 1200 1500 0 20 40 60 80 100 120 140 r t (k ) frequency (khz ) 0.98 0.99 1.00 1.01 1.02 -50 0 50 100 150 temperature ( o c) frequency figure 6. frequency vs. r t figure 7. frequency vs. temperature, normalized 0.60 0.80 1.00 1.20 1.40 1.60 -50 0 50 100 15 0 temperature ( o c) r ds 0.96 0.98 1.00 1.02 1.04 -50 0 50 100 150 temperature ( o c) i ilim figure 8. r ds vs. temperature, normalized (v cc = v gs = 5 v) figure 9. i lim current (i ilim ) vs. temperature, normalized q1 ~0.32 %/ o c q2 ~0.35 %/ o c 300 khz 600 k hz
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan2106 ? rev. 1.1.2 8 fan2106 ? tinybuck? 3-24v input, 6a, high-effi ciency, integrated synchronous buck regulator application circuit figure 10. application circuit: 1.8 v out , 500 khz typical performance characteristics typical operating characteristics usi ng the circuit shown in figure 10. v in =12 v, v cc =5 v, unless otherwise specified. 70 75 80 85 90 95 100 0123456 load (a) efficiency (%) 0 200 400 600 800 1000 1200 1400 0123456 load (a) dissipation (mw) figure 11. 1.8 v out efficiency over v in vs. load figure 12. 1.8 v out dissipation over v in vs. load 70 75 80 85 90 95 100 0123456 load (a) efficiency (% ) 70 75 80 85 90 95 100 0123456 load (a) efficiency (% ) figure 13. 1.8 v out efficiency over frequency vs. load (circuit value changes) figure 14. 3.3 v out efficiency vs. load (circuit value changes) 8 v in 12 v in 18 v in 300 khz 500 k hz 700 khz 8 v in 12 v in 18 v in v in =12v 12v in , 500 k hz 8v in , 300 khz 18v in , 700 k hz fan2106
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan2106 ? rev. 1.1.2 9 fan2106 ? tinybuck? 3-24v input, 6a, high-effi ciency, integrated synchronous buck regulator typical performance characteristics (continued) typical operating characteristics usi ng the circuit shown in figure 10. v in =12 v, v cc =5 v, unless otherwise specified. figure 15. sw and v out ripple, 6 a load figure 16. startup with 1 v pre-bias on v out figure 17. transient response, 2-6 a load figure 18. re-start on fault figure 19. startup, 3 a load figure 20. shutdown, 3 a load v out sw v out sw i out sw v out en pgood pgood en en v out v out
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan2106 ? rev. 1.1.2 10 fan2106 ? tinybuck? 3-24v input, 6a, high-effi ciency, integrated synchronous buck regulator circuit description pwm generation refer to figure 2 for the pwm control mechanism. fan2106 uses the summing-m ode method of control to generate the pwm pulses. an amplified current-sense signal is summed with an internally generated ramp and the combined signal is compar ed with the output of the error amplifier to generate t he pulsewidth to drive the high-side mosfet. sensed curr ent from the previous cycle is used to modulate the output of the summing block. the output of the summing block is also compared against a voltage threshold set by the r lim resistor to limit the inducto r current on a cycle-by-cycle basis. the r ramp resistor helps set the charging current for the internal ramp and provides input voltage feed- forward function. the contro ller facilitates external compensation for enhanced flexibility. initialization once v cc exceeds the uvlo threshold and en is high, the ic checks for a shorted fb pin before releasing the internal soft-start ramp (ss). if the parallel combination of r1 and r bias is 1 k , the internal ss ramp is not re leased and the regulator does not start. enable fan2106 has an internal pull-up to the enable (en) pin so that the ic is enabled once v cc exceeds the uvlo threshold. connecting a small capacitor across en and agnd delays the rate of voltage rise on the en pin. the en pin also serves for the restart whenever a fault occurs (refer to the auto-restart section) . if the regulator is enabled externally, the external en signal should go high only after v cc is established. for applications where such sequencing is required, fan2106 can be enabled (after the v cc comes up) with external control, as shown in figure 21. figure 21. enabling with external control soft-start once internal ss ramp has charged to 0.8 v (t0.8), the output voltage is in regulati on. until ss ramp reaches 1.0 v (t1.0), the fault latch is inhibited. to avoid skipping the soft-start cycle, it is necessary to apply v in before v cc reaches its uvlo threshold. normal sequence for powering up would be vin ? vcc ? en. soft-start time is a function of switching frequency. ss 1.35v fb en 0.8v t0.8 t1.0 3200 clks 4000 clks fault latc h enable 0.8v 1.0v 2400 clks figure 22. soft-start timing diagram cycling v cc or the en pin discharges the internal ss and resets the ic. in applications where external en signal is used, v in and v cc should be established before the en signal comes up to prevent skipping the soft- start function. startup on pre-bias the regulator does not allow the low-side mosfet to operate in full synchronous rectification mode until internal ss ramp reaches 95% of v ref (~0.76 v). this helps the regulator star t on a pre-biased output and ensures that the pre-bias ed outputs are not discharged during soft-start. protections the converter output is m onitored and protected against extreme overload, short-ci rcuit, over-voltage, under- voltage, and over-tem perature conditions. under-voltage shutdown if the voltage on the fb pin remains below the under- voltage threshold for 16 consecutive clock cycles, the fault latch is set and the c onverter shuts down. this protection is not active until the internal ss ramp reaches 1.0 v during soft-start. over-voltage protection if voltage on the fb pin exceeds 115% of v ref for two consecutive clock cycles, the fault latch is set and shutdown occurs. a shorted high-side mosfet condition is detected when sw voltage exceeds ~0.7 v while the low-side
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan2106 ? rev. 1.1.2 11 fan2106 ? tinybuck? 3-24v input, 6a, high-effi ciency, integrated synchronous buck regulator mosfet is fully enhanced. the fault latch is set immediately upon detection. the ov and high-side short fault protections are active all the time, including during soft-start. over-temperature protection (otp) the chip incorporates an over-temperature protection circuit that sets the fault la tch when a die temperature of about 150c is reached. the ic restarts when the die temperature falls below 125c. auto-restart after a fault, en pin is discharged by a 1 a current sink to a 1.1 v threshold before the internal 800 k pull-up is restored. a new soft-start cycle begins when en charges above 1.35 v. depending on the external circuit, the fan2106 can be configured to remain latched-off or to automatically restart after a fault. table 1. fault / restart configurations en pin controller / restart state pull to gnd off (disabled) pull-up to v cc with 100 k no restart ? latched off (after v cc comes up) open immediate restart after fault cap. to gnd new soft-start cycle after: t delay (ms)=3.9 ? c(nf) when en is left open, restart is immediate. if auto-restart is not desired, tie the en pin to the vcc pin or pull it high after v cc comes up with a logic gate to keep the 1 a current sink from discharging en to 1.1 v. figure 23 shows one method to pull up en to v cc for a latch configuration. 14 fan2106 15 100k en vcc 3.3n figure 23. enable control with latch option power-good (pgood) signal pgood is an open-drain output that asserts low when v out is out of regulation, as measured at the fb pin. thresholds are specified in t he electrical specifications section. pgood does not a ssert high until the fault latch is enabled (t1.0) (see figure 22) . application information bias supply the fan2106 requires a 5 v supply rail to bias the ic and provide gate-drive energy. connect a 1.0 f x5r or x7r decoupling capacit or between vcc and pgnd. since v cc is used to drive the internal mosfet gates, supply current is frequency and voltage dependent. approximate v cc current (i cc ) can be calculated using: )] 128 f ( ) 013 . 0 227 5 v [( 58 . 4 i cc ) ma ( cc ? ? + ? + = (1) where frequency (f) is expressed in khz. setting the output voltage the output voltage of the r egulator can be set from 0.8 v to 80% of v in by an external resistor divider (r1 and r bias in figure 1). for output voltages > 5 v, output current rating may need to be de-rated depending upon the ambient temperature, power dissipated in the package and the pcb layout. the external resistor divider is calculated using: na 650 1 r v 8 . 0 v r v 8 . 0 out bias + ? = (2) connect r bias between fb and agnd. if r1 is open (see figure 1), the output voltage is not regulated eventually causing a latched fault after the soft start is complete (t1.0) if the parallel combination of r1 and r bias is 1k , the internal ss ramp is not released and the regulator does not start. setting the switching frequency switching frequency is determined by an external resistor, r t, connected between the r(t) pin and agnd: 65 135 ) f / 10 ( r 6 ) k ( t ? = (3) where r t is in k and frequency (f) is in khz. the regulator cannot start if r t is left open. calculating the inductor value typically the inductor value is chosen based on ripple current ( il), which is chosen between 10 to 35% of the maximum dc load. regulator designs that require fast transient response use a higher ripple-current setting, while regulator designs that require higher efficiency keep ripple current on the low side and operate at a lower switching frequency. the inductor value is calculated by the following formula: f l d) - (1 v i out l ? ? = (4) where f is the switching frequency.
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan2106 ? rev. 1.1.2 12 fan2106 ? tinybuck? 3-24v input, 6a, high-effi ciency, integrated synchronous buck regulator setting the ramp resistor value r ramp resistor plays a critical role in the design by providing charging current to the internal ramp capacitor and also serving as a means to provide input voltage feedforward. r ramp is calculated by the following formula: 2 10 ) 18 ( ) 8 . 1 ( 6 ) ( ? ? ? ? ? ? = ? f v v v r in out in k ramp (5) where frequency (f) is expressed in khz. for wide input operation, first calculate r ramp for the minimum and maximum input voltage conditions and use larger of the two values calculated. in all applications, current through the r ramp pin must be greater than 10 a from the equation below for proper operation: a r v ramp in 10 2 8 . 1 + ? (6) if the calculated r ramp values in equation (5) result in a current less than 10 a, use the r ramp value that satisfies equation (6). in applications with large input ripple voltage, the r ramp resistor should be adequately decoupled from the input voltage to minimize ripple on the ramp pin . setting the current limit the current limit system involves two comparators. the max i limit comparator is used with a v ilim fixed-voltage reference and represents the maximum current limit allowable. this reference voltage is temperature compensated to reflect the r dson variation of the low- side mosfet. the adjust i limit comparator is used where the current limit needs to be set lower than the v ilim fixed reference. the 10 a current source does not track the r dson changes over temperature, so change is added into the equations for calculating the adjust i limit comparator reference voltage, as is shown below. figure 24 shows a simplified schematic of the over- current system. figure 24. current-limit system schematic since the i lim voltage is set by a 10 a current source into the r ilim resistor, the basic equation for setting the reference voltage is: v rilim = 10a*r ilim (7) to calculate r ilim : r ilim = v rilim / 10a (8) the voltage v rilim is made up of two components, v bot (which relates to the current through the low-side mosfet) and v rmpeak (which relates to the peak current through the inductor). combining those two voltage terms results in: r ilim = (v bot + v rmpeak )/ 10a (9) r ilim = {0.96 + (i load * r dson *k t *8)} + {d*(v in ? 1.8)/(f sw *0.03*r ramp )}/10a (10) where: v bot = 0.96 + (i load * r dson *k t *8); v rmpeak = d*(v in ? 1.8)/(f sw *0.03*r ramp ); i load = the desired maximum load current; r dson = the nominal r dson of the low-side mosfet; k t = the normalized temperature coefficient for the low-side mosfet (on datasheet graph); d = v out /v in duty cycle; f sw = clock frequency in khz; and r ramp = chosen ramp resistor value in k . after 16 consecutive, pulse-by-pulse, current-limit cycles, the fault latch is set and the regulator shuts down. cycling v cc or en restores operation after a normal soft-start cycle (refer to the auto-restart section) . the over-current protection fault latch is active during the soft-start cycle. use 1% resistor for r ilim . + _ v cc 1 0a ilimit ilim rilim + _ ilimit adjust max + _ comp pwm verr pwm ilimtrip vilim ramp
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan2106 ? rev. 1.1.2 13 fan2106 ? tinybuck? 3-24v input, 6a, high-effi ciency, integrated synchronous buck regulator loop compensation the loop is compensated using a feedback network around the error amplifier. figure 25 shows a complete type-3 compensation network. for type-2 compensation, eliminate r3 and c3. figure 25. compensation network since the fan2106 employs a summing current-mode architecture, type-2 compensation can be used for many applications. for applications that require wide loop bandwidth and/or use very low-esr output capacitors, type-3 compensation may be required. r ramp also provides feedforward compensation for changes in v in . with a fixed r ramp value, the modulator gain increases as v in is reduced; this could make it difficult to compensate the loop. for low-input-voltage- range designs (3 v to 8 v), r ramp and the compensation component values are different compared to designs with v in between 8 v and 24 v. application note an-8022 (tinycalc?) can be used to calculate the compensation components. recommended pcb layout good pcb layout and careful attention to temperature rise is essential for reliable operation of the regulator. four-layer pcb with two-ounce copper on the top and bottom sides and thermal vias connecting the layers are recommended. keep power traces wide and short to minimize losses and ringing. do not connect agnd to pgnd below the ic. connect the agnd pin to pgnd at the output or to the pgnd plane. v in gnd sw v out gnd figure 26. recommended pcb layout
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan2106 ? rev. 1.1.2 14 fan2106 ? tinybuck? 3-24v input, 6a, high-effi ciency, integrated synchronous buck regulator physical dimensions a) dimensions are in millimeters. b) dimensions and tolerances per asme y14.5m, 1994 top view bottom view recommended land pattern 2x 2x side view seating plane c) dimensions do not include mold flash or burrs. f) drawing filename: mkt-mlp25arev3 d) design based on jedec mo-220 variation wjhc all values typical except where noted e) terminals are symmetrical around the x & y axis except where depopulated. optional lead design (leads# 1, 24 & 25 only) scale: 1.5x figure 27. 5x6mm molded leadless package (mlp) package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan2106 ? rev. 1.1.2 15 fan2106 ? tinybuck? 3-24v input, 6a, high effi ciency, integrated synchronous buck regulator

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